Typical clock distribution schemes include a clock generation circuit integrated with a memory array to provide a clock signal which controls the internal operations of the memory array. This array clock is conventionally generated from a system clock, and typically has a pulse width which is dependent upon the frequency of the system clock.
There are two portions to an array clock, i.e., an active portion and an inactive (or reset) portion. During the active portion of the array clock cycle, the memory array is accessed and read or write operations are performed. During the inactive portion of the array clock cycle, the internal timings of the memory array are reset to a predetermined state. For the array to function properly, there should be an adequate amount of active clock time and an adequate amount of inactive clock time. An excess amount of either will result in wasted cycle time, or frequency, while an insufficient amount of either will result in failure of the circuit.
Ideally, there is a small amount of margin in both the active and inactive portions of the clock cycle to balance a maximum operational frequency with a robust design point. The robust design point is required to account for process and environmental variations and tolerances across circuits within the given memory array to allow for a reasonable yield. Thus, provided herein is a novel clock control method and apparatus for a memory array which addresses these concerns.